1. Field of the Invention
The present invention relates to a frequency synthesizer for generating signals having desired frequencies in synchronization with a reference signal having a reference frequency.
2. Description of the Related Art
A phase locked loop (PLL) to which highly advanced electronic circuit techniques and digital signal processing techniques are applied is being widely used for not only household electric appliances but also trunk line communication networks and communication apparatuses where synchronization among signals must be stably maintained with high precision. This is because the PLL can be stably and synergistically implemented with the following advantages.                To be easily and flexibly adapted to a very wide range of frequency bands in a digital domain.        To be flexibly adapted to variations and inequalities of temperature, operation voltages and other environmental conditions.        To make adjustments easy.        To stably achieve and maintain desired performance even when the precision of components is not substantially high.        
FIG. 10 is a diagram illustrating a first configuration example of a frequency synthesizer having a phase locked loop.
As shown in the figure, a reference signal having a reference frequency fr (herein assumed to be 8 KHz) is stationarily inputted to one input terminal of a digital phase detector (DPD) 41 whose output terminal is connected to an input terminal of a voltage controlled oscillator (VCO) 43 via a digital signal processor (DSP) 42. An output signal having a desired frequency F (herein assumed to be 3.24 MHz) is obtained from an output terminal of the voltage controlled oscillator 43 and is inputted to input terminals of a pre-scaler 44 and a clock signal generator 45. An output terminal of the pre-scaler 44 is connected to the other input terminal of the digital phase detector 41 and an output terminal of the clock signal generator 45 is connected to a clock terminal of the digital phase detector 41.
In the frequency synthesizer as configured above, the clock signal generator 45 multiplies an output signal outputted from the voltage controlled oscillator 43 by a predefined multiplication ratio m (=24=77.76×106/(3.24×106)) to thereby generate a clock signal having a predefined frequency fc (herein assumed to be 77.76 MHz).
In addition, a pre-scaler 44 divides an output signal outputted from the voltage controlled oscillator 43 by a predefined division ratio d (=405=3.24×106/(8×103)) to thereby generate a feedback signal.
A digital phase detector 41 detects a phase difference Δθ between the reference signal and the feedback signal at a point of a leading edge (or a trailing edge) of the clock signal.
A digital signal processor 42 integrates a series of phase differences Δθ detected as described above every time τ (=4 ms=1/(8×103)×32) that is 32 times a period (=1/fr) of a reference signal, removes undesired harmonic components included in a result of the integration, and accordingly, maintains an instantaneous voltage value Vc of a control signal, which is to be provided to the voltage controlled oscillator 43, at a value where a phase difference Δθ of the control signal is compressed.
Accordingly, as long as a frequency fr of a reference signal is precisely maintained at a desired value and a proper division ratio d and a multiplication ratio m are set in the pre-scaler 44 and the clock signal generator 45, respectively, a frequency F of an output signal generated from the voltage controlled oscillator 43 can be maintained at a desired frequency F (=3.24 MHz) precisely and stably.
FIG. 11 is a diagram illustrating a second configuration example of a frequency synthesizer having a phase locked loop.
The configuration of the frequency synthesizer shown in FIG. 11 is different from that of the frequency synthesizer shown in FIG. 10 (hereinafter referred to as first conventional example) in the following respects.                A digital signal processor 42 and a clock signal generator 45 are replaced with a digital signal processor (DSP) 42A and a clock signal generator 45A, respectively.        A local reference signal oscillator (OSC) 51 is added.        An output terminal of the local reference signal oscillator (OSC) 51, in stead of the output terminal of the voltage controlled oscillator 43, is connected to an input terminal of the clock signal generator 45A.        The voltage controlled oscillator 43 is replaced with a direct frequency synthesizer (DDS) 53 having two input terminals connected respectively to an output terminal of the digital signal processor 42A and the output terminal of the local reference signal oscillator 51 and a low pass filter (LPF) 52 cascaded at a subsequent stage.        
In the frequency synthesizer as configured above (hereinafter referred to as second conventional example), the clock signal generator 45A divides a frequency of a local reference signal (herein assumed that the frequency is fL) generated from the local reference signal oscillator 51 by a division ratio d′ suitable for a frequency of the local reference signal to thereby generate a clock signal having the frequency fc as mentioned above.
In addition, the digital signal processor 42A provides a instantaneous value Vc of the control signal as mentioned above to the direct frequency synthesizer (DDS) 53, as a series of values adapted to characteristics of the direct frequency synthesizer 53 and at which a frequency F of the output signal generated from the direct frequency synthesizer 53 and the low pass filter 52 is maintained at desired values.
Accordingly, a frequency of an output signal is precisely and stably maintained at a desired value F in the same manner as in the first conventional example.
However, in the first conventional example, for example, improvement of the precision and stability of the frequency F of the output signal can be achieved only when the precision of the phase difference Δθ detected by the digital phase detector 41 is sufficiently high. To this end, the frequency fc of the clock signal provided to the digital phase detector 41 must be set to a high value.
However, in order to set the frequency fc of the clock signal to a high value, the clock signal generators 45 and 45A must employ devices or circuits which can operate at such a high frequency that the frequency fc can be sufficiently achieved.
Accordingly, actually, it is substantially difficult to improve a precision of a frequency of an output signal under restriction on costs, power consumption, thermal design and other factors.
In addition, in the first conventional example, a clock signal is generated by dividing (or multiplying) a frequency of an output signal directly, as described above. Accordingly, for example, if a frequency fr of a reference signal is inadequately shifted or varied, a clock signal is maintained at a frequency in proportion to the improper frequency.
Accordingly, it is difficult to determine regularity of the frequency fr of a reference signal unless a separate monitoring section is added.